1. Field of the Invention
This invention relates generally to memory devices, and more particularly, to an approach for reducing exposure of such a device to hydrogen in formation of a silicon nitride layer.
2. Discussion of the Related Art
FIG. 1 illustrates a flash memory cell 20 (as part of a wafer) in accordance with the prior art. As such, the cell on 20 in the form of a transistor includes a semiconductor substrate 22 in which source/drains 24, 26 are formed. Successive layers of gate dielectric 28, storage layer 30, dielectric 32 and control gate 34 are formed on the substrate 22. Silicide layers 36, 38, 40 are formed on the source/drains 24, 26 and the control gate 34. The memory cell 20 is programmable, upon application of appropriate voltages, by moving electrons from a source/drain through the gate dielectric 28 and into the storage layer 30, where such electrons are stored. The memory cell 20 is erasable, again upon application of appropriate voltages, by removing electrons from the storage layer 30 through the gate dielectric 28 and into a source/drain, as is well known.
Overlying this structure is a BPSG (or PSG) insulating layer 42. A tungsten body 44 extends through the layer 42 and in contact with silicide layer 36. Another tungsten body 46 extends through the layer 42 and in contact with silicide layer 40. A silicon dioxide (SiO2) layer 48 is patterned as shown over the thus described structure, and copper 50 is deposited on the resulting structure, in contact with the tungsten bodies 44, 46.
Next, with reference to FIG. 2, a chemical-mechanical polishing (CMP) step is undertaken to planarize the structure, removing copper from over the SiO2 layer 48 and leaving copper bodies 52, 54 in contact with the respective tungsten bodies 44, 46, forming respective conductors 56, 58. With reference to FIG. 3, in a relatively short period of time, exposure of the thus-formed structure to the atmosphere causes exposed copper of the copper bodies 52, 54 to oxidize, forming copper oxide (CuO2) layers 60, 62 on the respective copper bodies 52, 54. These copper oxide layers 60, 62, if allowed to remain in place, can result in poor adhesion between the copper bodies 52, 54 and a silicon nitride (SiN) layer formed thereon, due to poor copper-silicon bonding at the interface thereof. This in turn results in poor electro-migration and stress-migration performance. In addition, traces of copper may remain on the SiO2 layer 48 after the CMP step, and copper can also readily migrate from the copper bodies 52, 54 onto the top surface of the layer 42. This can result in undesired current leakage between adjacent conductors 56, 58. Indeed, as devices shrink in size with continued progress in technology, the distance between the conductors decreases, increasing the likelihood of undesired conductor-to-conductor leakage.
To overcome this problem, a plasma-enhanced pre-treatment step is undertaken as illustrated in FIG. 4. The thus far formed structure (as part of a wafer) is placed on and heated by a heater 66 in a chamber 68, and ammonia (NH3) is drawn into the chamber 68 by vacuum pump 70. RF power is applied into the chamber 68 so that a plasma etch is undertaken, removing the copper oxide 60, 62 from the copper bodies 52, 54 and removing the copper from the top surface of the BPSG layer 42.
Next, and with reference to FIG. 5, with the structure still being heated by the heater in the chamber, silane (SiH4), ammonia (NH3), and nitrogen (N2, dilutant) are drawn into the chamber 68 by vacuum pump 70. RF power is applied into the chamber 68, and through these steps, a silicon nitride layer 72 is formed on the resulting structure by plasma-enhanced deposition, in contact with the copper bodies 52, 54 and SiO2 layer 48.
While these steps are effective for their purpose (i.e., good removal of copper oxide from the copper bodies 52, 54 and good removal of copper from the upper surface of the SiO2 layer 48 is achieved by the plasma-enhanced treatment step of FIG. 4, and good Cu—Si bonding is achieved at the interface of the copper-silicon nitride in plasma-enhanced deposition of the silicon nitride layer 72 as in FIG. 5), a significant amount of hydrogen is involved in the overall process (contained in the ammonia in plasma-enhanced operations of the FIGS. 4 and 5 and in the silane of the operation of FIG. 5), and the plasma-enhanced operations of FIGS. 4 and 5 excite hydrogen of the ammonia and silane to form a significant amount of highly reactive hydrogen radicals, which can readily penetrate the BPSG (or PSG) layer 42 and the transistor 20 itself, resulting in decreased memory cell performance. In addition, depending on the present conditions, a significant amount of silicon-hydrogen bonding can exist in the silicon nitride layer 72, which has been found to result in degraded device cycling and charge loss/charge gain data.
Reduction of silane flow in the step of FIG. 5 reduces formation of hydrogen radicals, which in turn reduces silicon-hydrogen bonding in the silicon nitride layer 72, lessening the problems caused thereby. However, this also results in reduced Cu—Si bonding at the silicon nitride-copper interface, which reduces adhesion between the copper bodies 52, 54 and the silicon nitride layer 72.
Therefore, what is needed is an approach wherein a proper structure is formed, meanwhile with reduced exposure of the structure to hydrogen radicals, and meanwhile achieving good Cu—Si bonding at the silicon nitride-copper interface for good adhesion of the silicon nitride layer 72 to the copper bodies 52, 54, so as to improve performance thereof as compared to the above-described the approach.